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CS5467
DIGITAL CHARACTERISTICS
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Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions .
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
DCLK = 4.096 MHz.
Parameter Symbol
Min
Typ
Max
Unit
Master Clock Characteristics
Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Internal Gate Oscillator (Note 11)
(Note 12 and 13)
DCLK
2.5
40
40
4.096
-
-
20
60
60
MHz
%
%
Filter Characteristics
Phase Compensation Range
Input Sampling Rate
(60 Hz, OWR = 4000 Hz)
DCLK = MCLK/K
-5.4
-
-
DCLK/8
+5.4
-
°
Hz
Digital Filter Output Word Rate
High-pass Filter Corner Frequency
(Both channels)
-3 dB
OWR
-
-
DCLK/1024
0.5
-
-
Hz
Hz
Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR
Channel-to-channel Time-shift Error
(Note 15)
25
-
1.0
100
%FS
μs
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V IH
0.6 VD+
(VD+) – 0.5
0.8 ? VD+
-
-
-
-
-
-
V
V
V
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V IL
-
-
-
-
-
-
0.8
1.5
0.2 ? VD+
V
V
V
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V IL
-
-
-
-
-
-
0.48
0.3
0.2 ? VD+
V
V
V
High-level Output Voltage
I out = +5 mA
V OH
(VD+) - 1.0
-
-
V
Low-level Output Voltage
I out = -5 mA (VD = +5V)
I out = -2.5 mA (VD = +3.3V)
V OL
-
-
-
-
0.4
0.4
V
V
Input Leakage Current
3-state Leakage Current
Digital Output Pin Capacitance
(Note 16)
I in
I OZ
C out
-
-
-
±1
-
5
±10
±10
-
μA
μA
pF
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is
used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
limited by the full-scale signal applied to the input.
15. Configuration register ( Config ) bits PC[6:0] are set to “0000000”.
10
16.
The MODE pin is pulled low by an internal resistor.
DS714F3
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